目前分類:電子技術 (4)

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Silicon Laboratories 日前發表業界最高性能的嵌入式無線方案,包括EZRadioPRO 系列和 C8051F9xx 系列低功耗單片機(MCU)。EZRadioPRO嵌入式無線產品系列具有最大的單芯片輸出功率(高達+20 dBm),以及領先業界的靈敏度(-118 dBm),可提供最佳的鏈路質量,在持續擴大傳輸範圍的同時將功耗降至最低。

 

新 器件通過高性能及豐富的系統內置特性,例如封包處理和多樣性天線(antenna diversity),讓裝置能以最低的整體系統成本達到240至960MHz頻率。若搭配Silicon Labs的低功耗、低電壓C8051F9xx MCU系列,客戶便能開發僅需單顆電池即可運作的嵌入式無線方案,大幅減少諸如遠端讀表、家庭安防、遙控車門開關及建築自動化等消費性及工業應用的成本和 體積。

 

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孕龍科技(Zeroplus Technology)宣佈,已成功研發出3-Wrie、AC97Digi RF、SLE4442四種串列協議分析,均可利用孕龍邏輯分析儀進行解碼分析。

 

3-Wire主要應用於感測器或是時脈晶片的資料傳遞。透過3-Wire的傳輸,使得傳輸資料的電子電路體積可更加輕巧。AC97是常見的音訊處理晶片,主要應用在個人電腦或數位音響上,因為AC97功能強大,相對的應用範圍也相當廣大。

 

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11月17日在USB開發者會議上,廣泛採用的USB接口引來了新的3.0官方版本,會議上一些廠商希望採用該新標準的產品能達到400Mbyte/s。

 

USB 3.0在應用層上至少能達到300Mbyte/s的數據吞吐量。新規範與前代版本兼容,然而新接口需要新的線纜和連接器,而且傳輸距離被限制在3米,而目前的USB產品可以支持5米長的線纜。

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Embedded non-volatile memory (NVM) is becoming more prevalent in a wide range of chips, particularly for power-sensitive applications. Memory IP for such apps requires the design of both the basic memory bit and the memory macro architecture to minimise power demands. An appropriate one-time programmable (OTP) memory macro can meet NVM requirements while offering low-power operation.

Many applications that require NVM do not need hundreds or thousands of rewrite cycles. Code storage, calibration tables, setup parameters and the like seldom, if ever, need changing once programmed. For cases in which occasional change is required, an appropriate memory management algorithm can skip over outdated information and use previously empty memory to hold the updates. Such management lets a low-cost and secure antifuse-based OTP memory serve as a design's embedded memory just as effectively as a rewritable NVM.

The cost advantages of antifuse-based OTP memory stem from the cell size and process complexity. The antifuse memory's design can be as small as one transistor using technology such as Sidense's 1T-Fuse memory IP. The result is a memory cell area that is much smaller than floating-gate multi-time programmable memories. The small bit cell size results in a smaller memory array footprint, which in turn reduces the area-related cost of the die.

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